The Development Of Memory Modules

The state of the memory chip remained in use until the early days of the 286, which posed a practical obstacle to the development of computers due to its inability to be disassembled and replaced. In view of this, memory modules have emerged. Solder the memory chip onto a pre designed printed circuit board, and also use memory slots on the computer motherboard. This completely solves the problem of difficult installation and replacement of memory.
Before the release of the 80286 motherboard, memory was not valued by the world. At that time, memory was directly fixed on the motherboard and had a capacity of only 64-256KB. For the work programs running on PCs at that time, the performance and capacity of this type of memory were sufficient to meet the processing needs of software programs at that time. However, with the emergence of software programs and the new generation 80286 hardware platform, higher requirements for memory performance have been put forward by programs and hardware. In order to improve speed and expand capacity, memory must appear in an independent packaging form, thus giving birth to the concept of "memory module".
When the 80286 motherboard was first introduced, the memory module used the Single In line Memory Modules (SIMM) interface with a capacity of 30pin and 256kb. It must consist of 8 data bits and 1 checksum to form a bank. Therefore, the 30pin SIMM we see is usually used with four modules together. Since the PC entered the civilian market in 1982, the 30pin SIMM memory paired with the 80286 processor was the pioneer in the field of memory.
Subsequently, from 1988 to 1990, PC technology reached another peak of development, namely the 386 and 486 era. At this time, CPUs had already developed towards 16 bit, so 30 pin SIMM memory could no longer meet the demand. Its lower memory bandwidth had become an urgent bottleneck to be solved. Therefore, 72 pin SIMM memory appeared at this time, which supported 32-bit fast page mode memory and greatly increased memory bandwidth. The single capacity of 72 pin SIMM memory is generally 512KB to 2MB, and only two are required to be used simultaneously. Due to its incompatibility with 30pin SIMM memory, the PC industry decisively eliminated 30pin SIMM memory at this time.
EDO DRAM (Extended Date Out RAM) memory, which was a popular memory module between 1991 and 1995, is extremely similar to FP DRAM. It eliminates the time interval between the two storage cycles of extended data output memory and transfer memory, and accesses the next page while sending data to the CPU. Therefore, its speed is 15-30% faster than ordinary DRAM. The working voltage is generally 5V, the bandwidth is 32-bit, and the speed is above 40ns. It was mainly used on 486 and early Pentium computers at that time.
From 1991 to 1995, we witnessed an awkward situation where the development of memory technology was relatively slow and almost stagnant. Therefore, we saw the coexistence of 72 pin and 168 pin EDO RAM at this time. In fact, EDO memory also belongs to the category of 72 pin SIMM memory, but it adopts a completely new addressing method. EDO has made breakthroughs in cost and capacity, and with the rapid development of manufacturing processes, the capacity of a single EDO memory has now reached 4-16MB. Due to the fact that the data bus width of Pentium and higher level CPUs is 64 bits or even higher, both EDO RAM and FPM RAM must be used in pairs.
SDRAM era
After the release of the Intel Celeron series, AMD K6 processors, and related motherboard chipsets, EDO DRAM memory performance can no longer meet the needs. Memory technology must be thoroughly innovated to meet the requirements of the new generation CPU architecture. At this time, memory began to enter the classic SDRAM era.
The first generation of SDRAM memory was based on the PC66 specification, but soon due to the frequency dispute between Intel and AMD, the CPU external frequency was increased to 100MHz, so PC66 memory was quickly replaced by PC100 memory. With the advent of PIII and K7 era at 133MHz external frequency, the PC133 specification further improved the overall performance of SDRAM in the same way, with bandwidth increased to over 1GB/sec. Due to the 64 bit bandwidth of SDRAM, which corresponds to the 64 bit data bus width of the CPU, it only requires one memory to operate, further improving convenience. In terms of performance, due to its input and output signals being synchronized with the external frequency of the system, its speed significantly exceeds that of EDO memory.
It cannot be denied that SDRAM memory has evolved from the early 66MHz to 100MHz and 133MHz. Although it has not completely solved the bottleneck problem of memory bandwidth, CPU overclocking has become an eternal topic for DIY users. Therefore, many users overclock branded PC100 memory to 133MHz to achieve CPU overclocking success. It is worth mentioning that in order to facilitate the needs of some overclocking users, some PC150 and PC166 standard memory have emerged in the market.
Although the bandwidth of SDRAM PC133 memory can be increased to 1064MB/S, coupled with Intel's latest Pentium 4 plan, SDRAM PC133 memory cannot meet future development needs. At this time, Intel, in order to achieve market dominance, joined forces with Rambus to promote Rambus DRAM memory (known as RDRAM memory) in the PC market. Unlike SDRAM, it adopts a new generation of high-speed simple memory architecture based on a type of RISC (Reduced Instruction Set Computing) theory, which can reduce data complexity and improve overall system performance.
In the competition between AMD and Intel, this is the era of frequency competition, so the CPU clock speed is constantly increasing. Intel has launched high-frequency Pentium III and Pentium 4 processors to surpass AMD. Therefore, Rambus DRAM memory is seen by Intel as its future competitive killer. Rambus DRAM memory simplifies the data volume of each clock cycle with high clock frequency, so the memory bandwidth is quite excellent. For example, the PC 1066 1066 MHz 32-bit bandwidth can reach 4.2G Byte/sec, and Rambus DRAM was once considered a perfect match for Pentium 4.
However, despite this, the Rambus RDRAM memory was not born at the right time and still had to be "plundered" by higher speed DDR. At that time, the Rambus RDRAM memory of PC600 and PC700 was overshadowed by the Intel 820 chipset "error event", and the PC800 Rambus RDRAM was too expensive to gain the support of the Pentium 4 platform. Various problems caused the Rambus RDRAM to be stillborn. Rambus had hoped for PC166 standard RDRAM with higher frequency to turn the tide, but ultimately succumbed to DDR memory.
DDR era
DDR SDRAM (Dual DataRate SDRAM), also known as Double Rate SDRAM, is an upgraded version of SDRAM. DDR transfers data once on the rising and falling edges of the clock signal, which makes its data transfer speed twice that of traditional SDRAM. Due to the excessive use of falling edge signals, it does not result in an increase in energy consumption. As for addressing and control signals, they are the same as traditional SDRAM, only transmitted on the rising edge of the clock.
DDR memory is a compromise solution between performance and cost, aimed at quickly establishing a solid market space, gradually advancing in frequency, and ultimately compensating for the lack of memory bandwidth. The first generation DDR200 specification was not widely adopted, and the second generation PC266 DDR SRAM (133MHz clock x 2x data transfer=266MHz bandwidth) was derived from PC133 SDRAM memory, which brought DDR memory to the first peak. In addition, many Celeron and AMD K7 processors are using DDR266 specification memory, and its later DDR333 memory is also a transition. DDR400 memory has become the mainstream platform option, and dual channel DDR400 memory has become the basic standard for 800FSB processors. The subsequent DDR533 specification has become the choice of overclocking users.
DDR2 era
DDR2 (Double Data Rate 2) SDRAM is a new generation memory technology standard developed by JEDEC (Joint Electron Device Engineering Council). The biggest difference between DDR2 and the previous generation DDR memory technology standard is that although both use the basic method of data transfer simultaneously with clock rise/fall delay, DDR2 memory has twice the pre read capability of the previous generation DDR memory (i.e. 4-bit data read pre fetch). In other words, DDR2 memory can read/write data at 4 times the speed of the external bus per clock, and can run at 4 times the speed of the internal control bus.
In addition, due to the DDR2 standard, all DDR2 memories are packaged in FBGA, which is different from the widely used TSOP/TSOP-II packaging. FBGA packaging can provide better electrical performance and heat dissipation, providing a solid foundation for the stable operation and future frequency development of DDR2 memory. Looking back at the development history of DDR, from the first generation application of DDR200 to personal computers, through DDR266, DDR333 to dual channel DDR400 technology, the development of the first generation DDR has also reached the limit of technology, and it is difficult to improve the working speed of memory through conventional methods; With the development of Intel's latest processor technology, the demand for memory bandwidth in the front-end bus is increasing, and DDR2 memory with higher and more stable operating frequency will be the trend.
As CPU performance continues to improve, our requirements for memory performance are also gradually upgrading. It cannot be denied that DDR, which relies solely on high-frequency bandwidth enhancement, will eventually fall short. Therefore, the JEDEC organization has been brewing the DDR2 standard for a long time, and with the support of new platforms such as LGA775 interface 915/925 and the latest 945 for DDR2 memory, DDR2 memory will begin to explore the field of memory.
DDR2 can provide a minimum bandwidth of 400MB/s per pin based on a transmission frequency of 100MHz, and its interface will operate at a voltage of 1.8V, further reducing heat generation and increasing frequency. In addition, DDR2 will incorporate new performance indicators such as CAS, OCD, ODT, and interrupt instructions to improve the utilization of memory bandwidth. According to the DDR2 standard outlined by JEDEC organizers, DDR2 memory for markets such as PCs will have different clock frequencies such as 400, 533, and 667MHz. High end DDR2 memory will have two frequencies of 800 and 1000 MHz. DDR-II memory will be packaged in FBGA with 200-, 220-, and 240 pin configurations. The initial DDR2 memory will be produced using a 0.13-micron manufacturing process, with memory particles having a voltage of 1.8V and a capacity density of 512MB.
There is no doubt that memory technology will be popular in 2005, and static memory represented by SDRAM will not be popularized within five years. QBM and RDRAM memory are also unable to reverse their decline, so the coexistence of DDR and DDR2 will be an inevitable fact.
In addition to PC-133, VCM (VirXual Channel Memory) is also an important member of the successor of PC-100. VCM, also known as Virtual Channel Memory, is a memory standard supported by most newer chipsets. VCM memory is mainly manufactured based on a "cached DRAM" technology developed by NEC, which integrates "channel cache" and is configured and controlled by high-speed registers. While achieving high-speed data transmission, VCM also maintains high compatibility with traditional SDRAM, so VCM memory is commonly referred to as VCM SDRAM. The difference between VCM and SDRAM is that regardless of whether the data has been processed by the CPU or not, it can be first handed over to VCM for processing, while ordinary SDRAM can only process data processed by the CPU. Therefore, VCM processes data more than 20% faster than SDRAM. There are many chipsets that can support VCM SDRAM, including Intel's 815E, VIA's 694X, and so on.
RDRAM
After Intel launched the PC-100, due to technological advancements, the 800MB/s bandwidth of PC-100 memory was no longer sufficient to meet the demand, while the bandwidth improvement of PC-133 was not significant (1064MB/s), which also could not meet future development needs. In order to achieve the goal of monopolizing the market, Intel has partnered with Rambus to promote Rambus DRAM (DirectRambus DRAM) in the PC market, as shown in Figure 4-3.
Rambus DRAM is a memory specification first proposed by Rambus, which adopts a new generation of high-speed and simple memory architecture to reduce data complexity and improve overall system performance. Rambus uses a 400MHz 16 bit bus, which can transmit data simultaneously on the rising and falling edges within one clock cycle. Its actual speed is 400MHz × 2=800MHz, and its theoretical bandwidth is (16bit × 2 × 400MHz/8) 1.6GB/s, which is twice that of PC-100. In addition, Rambus can also store 9 bytes, with the additional bit being a reserved bit that may be used as an ECC (ErroI · Checking and Correction) checksum in the future. The clock of Rambus can reach up to 400MHz, and only 30 copper wires are used to connect the memory controller and RIMM (Rambus Inline Memory Modules). Reducing the length and quantity of copper wires can reduce electromagnetic interference in data transmission, thereby quickly increasing the operating frequency of the memory. However, at high frequencies, the heat it emits will definitely increase, so the first Rambus memory even needs to come with a built-in cooling fan.
DDR3 era
Compared to DDR2, DDR3 has a lower operating voltage, dropping from 1.8V to 1.5V, resulting in better performance and greater power savings; Upgrade the 4-bit read ahead of DDR2 to 8-bit read ahead. DDR3 can reach a maximum speed of 2400MHz, and as the fastest DDR2 memory speed has been increased to 800MHz/1066MHz, the first batch of DDR3 memory modules will jump from 800MHz. At the Computex exhibition, we saw multiple memory manufacturers showcasing 1333MHz DDR3 modules.
DDR3 adopts a new design based on DDR2:
1.8bit prefetching design, while DDR2 uses 4-bit prefetching, so the frequency of the DRAM core is only 1/8 of the interface frequency, and the core operating frequency of DDR3-800 is only 100MHz.
2. Adopt a point-to-point topology architecture to alleviate the burden on address/command and control buses.
3. Adopting a production process below 100nm, the working voltage is reduced from 1.8V to 1.5V, and asynchronous reset and ZQ calibration functions are added.
DDR4 era
DDR4 memory will have two specifications. The transfer rate of DDR4 memory using Single ended Signaling signal has been confirmed to be 1.6-3.2Gbps, while DDR4 memory based on differential signaling technology can achieve a transfer rate of 6.4Gbps. Due to the impossibility of implementing two interfaces through a single DRAM, DDR4 memory will have two specifications based on traditional SE signals and differential signals simultaneously.
According to several semiconductor industry professionals, DDR4 memory will be a combination of Single ended Signaling (traditional SE signal) and Differential Signaling (differential signal technology). It is expected that these two standards will introduce different chip products, so in the DDR4 memory era, we will see two incompatible memory products.